Analytical and Numerical Modeling of Self-Heating Effects in Nanoelectronic Devices

As transistor dimensions continue to shrink and device architectures evolve toward fully three-dimensional structures with dense nanoscale features, power dissipation and self-heating have emerged as critical challenges to sustaining performance and reliability. This thesis investigates the thermal behavior of advanced Fully Depleted Silicon-on-Insulator (FDSOI) and FinFET transistors, which represent manufacturable solutions to the scaling limitations of conventional planar MOSFETs, particularly with respect to short-channel effects. The work begins with an overview of scaling-induced constraints, most notably power dissipation, that have motivated the transition to multi-gate devices such as FinFETs and, in the future, nanosheet and complementary FET (CFET) architectures. \\ Fundamental mechanisms of heat transfer are reviewed, with particular emphasis on conduction, the dominant mode in semiconductor devices. Equivalent thermal network models are introduced to capture device heating within a compact, circuit-based framework, offering a practical approach for integrating thermal considerations into electronic design. The core of the study involves thermal simulations using Raphael, part of the Synopsys Sentaurus TCAD suite. Both steady-state and transient regimes are explored, with a particular focus on transient thermal dynamics, which remain insufficiently addressed in the literature. Initial analyses on simple one-dimensional slab geometries establish confidence in the methodology before advancing to simulations of FinFET and FDSOI devices. The results provide insight into temperature distribution, hot-spot formation, thermal resistance, and thermal capacitance, while also addressing the extraction of lumped thermal parameters from device geometry and physics rather than empirical assumptions.