Compact Modeling of Advanced RRAM Technology for 130 nm CMOS PDK Integration

Resistive Random-Access Memories (RRAMs) are promising devices for developing energy-efficient hardware, particularly for edge computing, in-memory computing, and neuromorphic circuits. Their programmable nonvolatile resistance enables multilevel operation, which can reduce both the area and energy consumption of RRAM-based vector-matrix multiplication (VMM) accelerators. At the same time, RRAM-based neuromorphic circuits can operate across vastly different timescales—from rapid switching events to slower synaptic dynamics. This diversity of operating conditions demands accurate and flexible compact models to guide circuit design and optimization. Yet modeling device behavior across all these scenarios remains genuinely challenging. The multilevel behavior during the reset phase is reasonably well characterized, but only a handful of compact models can also capture the multilevel features of the set phase. Even more problematic, general-purpose models often cannot reproduce the same device behavior across different timescales using a single, self-consistent parameter set. The field also lacks straightforward, reliable, and automated procedures for extracting compact-model parameters from experimental measurements. This thesis extends the UniMORE physics-based RRAM compact model by introducing advanced variability features in Verilog-A, covering both Cycle-to-Cycle (C2C) and Device-to-Device (D2D) variability. An automated parameter-extraction workflow is developed to calibrate the model from experimental data, implemented through a coupled Cadence Virtuoso-MATLAB simulation on a high-performance computing (HPC) platform. The enhanced model is calibrated using a new experimental dataset from IHP 130 nm Al-doped HfO2 1T1R RRAM devices, examining both SG13S and SG13G2 transistor configurations. A key challenge lies in calibrating the model with the access transistor present, since its parasitic effects alter the actual voltage and current seen by the RRAM device. The experimental data also inform the calibration and validation of the proposed C2C module, which faithfully reproduces the random switching behavior captured in the measurements. The resulting model successfully reproduces device behavior across multilevel, multi-timescale, and multi-compliance-current conditions using a single parameter set. Combined with the automated calibration workflow and variability modules, this model provides a practical framework for device-circuit co-optimization and for designing advanced RRAM-based memory, VMM, and neuromorphic hardware.